Regarding a multilayered thin film laminated capacitor wherein electrode layers and dielectric layers are alternately laminated onto each other, a capacitor structure 110 illustrated in a sectional view of FIG. 9 and a top view of FIG. 10 has been hitherto suggested as an example.
In this capacitor structure 110, a lower electrode layer 116 is formed on an insulating layer 114 covering a substrate 112, and dielectric layers 118b, 120b, 122b and 124b and electrode layers 118a, 120a, 122a and 124a are alternately formed on the lower electrode layer 116. The whole of the lamination is covered with an insulating layer 126. The top view of FIG. 10 illustrates a situation that the insulating layer 126 is removed. The electrode layers and the dielectric layers constitute pairs 118a and 118b; 120a and 120b; 122a and 122b; and 124a and 124b. A higher pair of the pairs is smaller so that the pairs are piled in a stepwise pattern. The entire outer circumferences of the electrode layers 116, 118a, 120a and 122a protrude outwards, along the outer circumferences, from the electrode layer and dielectric layer pair 118a and 118b, 120a and 120b, 122a and 122b, and 124a and 124b, respectively, which are above the layers 116, 118a, 120a and 122a, respectively.
Connection parts 138, 140, 142, 144 and 146 connected to the electrode layers 116, 118a, 120a, 122a and 124a, respectively are exposed on the individual steps of the insulating layer 126. The respective connection parts 138, 140, 142, 144 and 146 are electrically connected to each other in an appropriate manner in accordance with a desired capacity characteristic (see, for example, Patent Document 1).
Patent Document: JP-T-2000-514243
When the stepwise capacitor structure 110 is formed, all layers that are to be the electrode layers and the dielectric layers are laminated and next the layers are etched step by step from the above to form the electrode layers and the dielectric layers in each step into desired forms. Thereafter, an insulating layer is formed thereon.
In a case where the number of the electrodes is N, at least (N−1) steps are required in order to make the upper surfaces of the electrode layers in each step exposed even when the electrode layer and the dielectric layer which correspond to a step are etched together. In order to conduct an etching operation, the following steps are generally experienced: the formation of a resist→exposure→development→etching→the removal of the resist. Moreover, a photomask becomes necessary for each of the layers. When the number of laminated layers is increased in order to increase the capacitance of the capacitor, steps therefor are added so that costs for the production increases remarkably.
Furthermore, the areas of the electrodes which constitute the capacitor by sandwiching a dielectric layer become smaller one layer by one layer as the positions of the electrodes are higher. Thus, even when the number of the laminated layers is increased, the capacitance is not varied very much.